1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to a high-k/metal gate transistor fabrication.
2. Background Art
To enable high performance complementary metal-oxide semiconductor (CMOS) technologies such as high dielectric constant (high-k) and metal gate solutions, a band-edge metal is required in the channel for each transistor to maximize performance and provide threshold voltages (Vt) appropriate for low voltage, low power technologies. Different band-edge metals in the channels have been shown to work for n-type field effect transistors (NFETs) and p-type FETs (PFETs). One challenge relative to fabricating these devices is preventing shifts in Vt during processing that occurs after initial formation.
Another challenge is to form both NFETs and PFETs together where each requires a different, or different concentration of, a band-edge metal. Typically, different, non-compatible, fabrication techniques are used. For example, one technique for certain PFETs includes using a thin epitaxially grown silicon germanium (SiGe) layer grown on top of a single crystal silicon layer to generate a SiGe channel for the PFET. The SiGe channel enables a shift of voltage from mid-gap to band-edge for the metal gate of the PFET, which improves performance. In contrast, for certain NFETs, a technique referred to as reverse embedded silicon germanium, i.e., reverse eSiGe, uses a plug of SiGe material embedded underneath the channel region of the device. The plug advantageously tensilely stresses the channel region which improves performance of the NFET. Current approaches to integrate both devices use multiple selective epitaxial growth processes for the different SiGe portions. That is, different selective epitaxial processes are used to grow the SiGe channel for PFETs, the SiGe plug for NFETS and perhaps SiGe source/drain regions. In addition, in some cases, an epitaxially grown silicon cap may be required on the SiGe plug of the NFETs and perhaps on the SiGe channel of the PFETs. The multiple epitaxial processes present a number of disadvantages such as added expense and poor throughput. In addition, each selective epitaxial growth process required presents a challenge regarding removal of any residual oxide that may form on the epitaxially grown area during exposure to the environment. More specifically, each epitaxially grown area may require an aqueous hydro-fluoric acid (HF) pre-clean and an in-situ hydrogen (H2) pre-bake prior to subsequent processing to remove any residual oxide, which may cause defects if not adequately removed. Since the temperature of the in-situ H2 pre-bake must be controlled to prevent damage to any previously formed sections, adequate oxide removal is challenging and oftentimes results in non-uniformity issues. Further non-uniformity and complexity issues are presented by the selective epitaxial growth processes in that the morphology of the sections being formed, and the edge effects of the sections, is defined by the openings into which the epitaxy is performed.